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Espressif Systems /ESP32-P4 /LP_I2S0 /CLK_GATE

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Interpret as CLK_GATE

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CLK_EN)CLK_EN 0 (VAD_CG_FORCE_ON)VAD_CG_FORCE_ON 0 (RX_MEM_CG_FORCE_ON)RX_MEM_CG_FORCE_ON 0 (RX_REG_CG_FORCE_ON)RX_REG_CG_FORCE_ON

Description

Clock gate register

Fields

CLK_EN

set this bit to enable clock gate
VAD_CG_FORCE_ON

VAD clock gate force on register
RX_MEM_CG_FORCE_ON

I2S rx mem clock gate force on register
RX_REG_CG_FORCE_ON

I2S rx reg clock gate force on register

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data